| 1 |
/*- |
| 2 |
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD |
| 3 |
* |
| 4 |
* Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> |
| 5 |
* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
| 8 |
* modification, are permitted provided that the following conditions |
| 9 |
* are met: |
| 10 |
* 1. Redistributions of source code must retain the above copyright |
| 11 |
* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
| 13 |
* notice, this list of conditions and the following disclaimer in the |
| 14 |
* documentation and/or other materials provided with the distribution. |
| 15 |
* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 17 |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 18 |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 19 |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 20 |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 21 |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 23 |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 24 |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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|
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#include <sys/cdefs.h> |
| 29 |
__FBSDID("$FreeBSD$"); |
| 30 |
|
| 31 |
#include "opt_mmccam.h" |
| 32 |
|
| 33 |
#include <sys/param.h> |
| 34 |
#include <sys/systm.h> |
| 35 |
#include <sys/bus.h> |
| 36 |
#include <sys/kernel.h> |
| 37 |
#include <sys/lock.h> |
| 38 |
#include <sys/module.h> |
| 39 |
#include <sys/mutex.h> |
| 40 |
#include <sys/resource.h> |
| 41 |
#include <sys/rman.h> |
| 42 |
#include <sys/sysctl.h> |
| 43 |
#include <sys/taskqueue.h> |
| 44 |
|
| 45 |
#include <dev/pci/pcireg.h> |
| 46 |
#include <dev/pci/pcivar.h> |
| 47 |
|
| 48 |
#include <machine/bus.h> |
| 49 |
#include <machine/resource.h> |
| 50 |
|
| 51 |
#include <dev/mmc/bridge.h> |
| 52 |
|
| 53 |
#include <dev/sdhci/sdhci.h> |
| 54 |
|
| 55 |
#include "mmcbr_if.h" |
| 56 |
#include "sdhci_if.h" |
| 57 |
|
| 58 |
/* |
| 59 |
* PCI registers |
| 60 |
*/ |
| 61 |
#define PCI_SDHCI_IFPIO 0x00 |
| 62 |
#define PCI_SDHCI_IFDMA 0x01 |
| 63 |
#define PCI_SDHCI_IFVENDOR 0x02 |
| 64 |
|
| 65 |
#define PCI_SLOT_INFO 0x40 /* 8 bits */ |
| 66 |
#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) |
| 67 |
#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) |
| 68 |
|
| 69 |
/* |
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* RICOH specific PCI registers |
| 71 |
*/ |
| 72 |
#define SDHC_PCI_MODE_KEY 0xf9 |
| 73 |
#define SDHC_PCI_MODE 0x150 |
| 74 |
#define SDHC_PCI_MODE_SD20 0x10 |
| 75 |
#define SDHC_PCI_BASE_FREQ_KEY 0xfc |
| 76 |
#define SDHC_PCI_BASE_FREQ 0xe1 |
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|
| 78 |
static const struct sdhci_device { |
| 79 |
uint32_t model; |
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uint16_t subvendor; |
| 81 |
const char *desc; |
| 82 |
u_int quirks; |
| 83 |
} sdhci_devices[] = { |
| 84 |
{ 0x08221180, 0xffff, "RICOH R5C822 SD", |
| 85 |
SDHCI_QUIRK_FORCE_DMA }, |
| 86 |
{ 0xe8221180, 0xffff, "RICOH R5CE822 SD", |
| 87 |
SDHCI_QUIRK_FORCE_DMA | |
| 88 |
SDHCI_QUIRK_LOWER_FREQUENCY }, |
| 89 |
{ 0xe8231180, 0xffff, "RICOH R5CE823 SD", |
| 90 |
SDHCI_QUIRK_LOWER_FREQUENCY }, |
| 91 |
{ 0x8034104c, 0xffff, "TI XX21/XX11 SD", |
| 92 |
SDHCI_QUIRK_FORCE_DMA }, |
| 93 |
{ 0x05501524, 0xffff, "ENE CB712 SD", |
| 94 |
SDHCI_QUIRK_BROKEN_TIMINGS }, |
| 95 |
{ 0x05511524, 0xffff, "ENE CB712 SD 2", |
| 96 |
SDHCI_QUIRK_BROKEN_TIMINGS }, |
| 97 |
{ 0x07501524, 0xffff, "ENE CB714 SD", |
| 98 |
SDHCI_QUIRK_RESET_ON_IOS | |
| 99 |
SDHCI_QUIRK_BROKEN_TIMINGS }, |
| 100 |
{ 0x07511524, 0xffff, "ENE CB714 SD 2", |
| 101 |
SDHCI_QUIRK_RESET_ON_IOS | |
| 102 |
SDHCI_QUIRK_BROKEN_TIMINGS }, |
| 103 |
{ 0x410111ab, 0xffff, "Marvell CaFe SD", |
| 104 |
SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, |
| 105 |
{ 0x2381197B, 0xffff, "JMicron JMB38X SD", |
| 106 |
SDHCI_QUIRK_32BIT_DMA_SIZE | |
| 107 |
SDHCI_QUIRK_RESET_AFTER_REQUEST }, |
| 108 |
{ 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", |
| 109 |
SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, |
| 110 |
{ 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", |
| 111 |
SDHCI_QUIRK_INTEL_POWER_UP_RESET | |
| 112 |
SDHCI_QUIRK_WAIT_WHILE_BUSY | |
| 113 |
SDHCI_QUIRK_MMC_DDR52 | |
| 114 |
SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | |
| 115 |
SDHCI_QUIRK_PRESET_VALUE_BROKEN}, |
| 116 |
{ 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", |
| 117 |
SDHCI_QUIRK_WAIT_WHILE_BUSY | |
| 118 |
SDHCI_QUIRK_PRESET_VALUE_BROKEN }, |
| 119 |
{ 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", |
| 120 |
SDHCI_QUIRK_INTEL_POWER_UP_RESET | |
| 121 |
SDHCI_QUIRK_WAIT_WHILE_BUSY | |
| 122 |
SDHCI_QUIRK_MMC_DDR52 | |
| 123 |
SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | |
| 124 |
SDHCI_QUIRK_PRESET_VALUE_BROKEN }, |
| 125 |
{ 0x19db8086, 0xffff, "Intel Denverton eMMC 5.0 Controller", |
| 126 |
SDHCI_QUIRK_INTEL_POWER_UP_RESET | |
| 127 |
SDHCI_QUIRK_WAIT_WHILE_BUSY | |
| 128 |
SDHCI_QUIRK_MMC_DDR52 | |
| 129 |
SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | |
| 130 |
SDHCI_QUIRK_PRESET_VALUE_BROKEN }, |
| 131 |
{ 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", |
| 132 |
SDHCI_QUIRK_DATA_TIMEOUT_1MHZ | |
| 133 |
SDHCI_QUIRK_INTEL_POWER_UP_RESET | |
| 134 |
SDHCI_QUIRK_WAIT_WHILE_BUSY | |
| 135 |
SDHCI_QUIRK_MMC_DDR52 | |
| 136 |
SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN }, |
| 138 |
{ 0x22968086, 0xffff, "Intel Braswell SDXC Controller", |
| 139 |
SDHCI_QUIRK_WAIT_WHILE_BUSY | |
| 140 |
SDHCI_QUIRK_PRESET_VALUE_BROKEN }, |
| 141 |
{ 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller", |
| 142 |
SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ |
| 143 |
SDHCI_QUIRK_WAIT_WHILE_BUSY | |
| 144 |
SDHCI_QUIRK_PRESET_VALUE_BROKEN }, |
| 145 |
{ 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", |
| 146 |
SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ |
| 147 |
SDHCI_QUIRK_INTEL_POWER_UP_RESET | |
| 148 |
SDHCI_QUIRK_WAIT_WHILE_BUSY | |
| 149 |
SDHCI_QUIRK_MMC_DDR52 | |
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SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | |
| 151 |
SDHCI_QUIRK_PRESET_VALUE_BROKEN }, |
| 152 |
{ 0, 0xffff, NULL, |
| 153 |
0 } |
| 154 |
}; |
| 155 |
|
| 156 |
struct sdhci_pci_softc { |
| 157 |
u_int quirks; /* Chip specific quirks */ |
| 158 |
struct resource *irq_res; /* IRQ resource */ |
| 159 |
void *intrhand; /* Interrupt handle */ |
| 160 |
|
| 161 |
int num_slots; /* Number of slots on this controller */ |
| 162 |
struct sdhci_slot slots[6]; |
| 163 |
struct resource *mem_res[6]; /* Memory resource */ |
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uint8_t cfg_freq; /* Saved frequency */ |
| 165 |
uint8_t cfg_mode; /* Saved mode */ |
| 166 |
}; |
| 167 |
|
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static int sdhci_enable_msi = 1; |
| 169 |
SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, |
| 170 |
0, "Enable MSI interrupts"); |
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|
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static uint8_t |
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sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) |
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{ |
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struct sdhci_pci_softc *sc = device_get_softc(dev); |
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|
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bus_barrier(sc->mem_res[slot->num], 0, 0xFF, |
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); |
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return bus_read_1(sc->mem_res[slot->num], off); |
| 180 |
} |
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|
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static void |
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sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused, |
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bus_size_t off, uint8_t val) |
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{ |
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struct sdhci_pci_softc *sc = device_get_softc(dev); |
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|
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bus_barrier(sc->mem_res[slot->num], 0, 0xFF, |
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); |
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bus_write_1(sc->mem_res[slot->num], off, val); |
| 191 |
} |
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|
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static uint16_t |
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sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) |
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{ |
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struct sdhci_pci_softc *sc = device_get_softc(dev); |
| 197 |
|
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bus_barrier(sc->mem_res[slot->num], 0, 0xFF, |
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); |
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return bus_read_2(sc->mem_res[slot->num], off); |
| 201 |
} |
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|
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static void |
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sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused, |
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bus_size_t off, uint16_t val) |
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{ |
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struct sdhci_pci_softc *sc = device_get_softc(dev); |
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|
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bus_barrier(sc->mem_res[slot->num], 0, 0xFF, |
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); |
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bus_write_2(sc->mem_res[slot->num], off, val); |
| 212 |
} |
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|
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static uint32_t |
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sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) |
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{ |
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struct sdhci_pci_softc *sc = device_get_softc(dev); |
| 218 |
|
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bus_barrier(sc->mem_res[slot->num], 0, 0xFF, |
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); |
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return bus_read_4(sc->mem_res[slot->num], off); |
| 222 |
} |
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|
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static void |
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sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused, |
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bus_size_t off, uint32_t val) |
| 227 |
{ |
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struct sdhci_pci_softc *sc = device_get_softc(dev); |
| 229 |
|
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bus_barrier(sc->mem_res[slot->num], 0, 0xFF, |
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); |
| 232 |
bus_write_4(sc->mem_res[slot->num], off, val); |
| 233 |
} |
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|
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static void |
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sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, |
| 237 |
bus_size_t off, uint32_t *data, bus_size_t count) |
| 238 |
{ |
| 239 |
struct sdhci_pci_softc *sc = device_get_softc(dev); |
| 240 |
|
| 241 |
bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); |
| 242 |
} |
| 243 |
|
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static void |
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sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, |
| 246 |
bus_size_t off, uint32_t *data, bus_size_t count) |
| 247 |
{ |
| 248 |
struct sdhci_pci_softc *sc = device_get_softc(dev); |
| 249 |
|
| 250 |
bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); |
| 251 |
} |
| 252 |
|
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static void sdhci_pci_intr(void *arg); |
| 254 |
|
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static void |
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sdhci_lower_frequency(device_t dev) |
| 257 |
{ |
| 258 |
struct sdhci_pci_softc *sc = device_get_softc(dev); |
| 259 |
|
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/* |
| 261 |
* Enable SD2.0 mode. |
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* NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. |
| 263 |
*/ |
| 264 |
pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); |
| 265 |
sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); |
| 266 |
pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); |
| 267 |
pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); |
| 268 |
|
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/* |
| 270 |
* Some SD/MMC cards don't work with the default base |
| 271 |
* clock frequency of 200 MHz. Lower it to 50 MHz. |
| 272 |
*/ |
| 273 |
pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); |
| 274 |
sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); |
| 275 |
pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); |
| 276 |
pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); |
| 277 |
} |
| 278 |
|
| 279 |
static void |
| 280 |
sdhci_restore_frequency(device_t dev) |
| 281 |
{ |
| 282 |
struct sdhci_pci_softc *sc = device_get_softc(dev); |
| 283 |
|
| 284 |
/* Restore mode. */ |
| 285 |
pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); |
| 286 |
pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); |
| 287 |
pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); |
| 288 |
|
| 289 |
/* Restore frequency. */ |
| 290 |
pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); |
| 291 |
pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); |
| 292 |
pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); |
| 293 |
} |
| 294 |
|
| 295 |
static int |
| 296 |
sdhci_pci_probe(device_t dev) |
| 297 |
{ |
| 298 |
uint32_t model; |
| 299 |
uint16_t subvendor; |
| 300 |
uint8_t class, subclass; |
| 301 |
int i, result; |
| 302 |
|
| 303 |
model = (uint32_t)pci_get_device(dev) << 16; |
| 304 |
model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; |
| 305 |
subvendor = pci_get_subvendor(dev); |
| 306 |
class = pci_get_class(dev); |
| 307 |
subclass = pci_get_subclass(dev); |
| 308 |
|
| 309 |
result = ENXIO; |
| 310 |
for (i = 0; sdhci_devices[i].model != 0; i++) { |
| 311 |
if (sdhci_devices[i].model == model && |
| 312 |
(sdhci_devices[i].subvendor == 0xffff || |
| 313 |
sdhci_devices[i].subvendor == subvendor)) { |
| 314 |
device_set_desc(dev, sdhci_devices[i].desc); |
| 315 |
result = BUS_PROBE_DEFAULT; |
| 316 |
break; |
| 317 |
} |
| 318 |
} |
| 319 |
if (result == ENXIO && class == PCIC_BASEPERIPH && |
| 320 |
subclass == PCIS_BASEPERIPH_SDHC) { |
| 321 |
device_set_desc(dev, "Generic SD HCI"); |
| 322 |
result = BUS_PROBE_GENERIC; |
| 323 |
} |
| 324 |
|
| 325 |
return (result); |
| 326 |
} |
| 327 |
|
| 328 |
static int |
| 329 |
sdhci_pci_attach(device_t dev) |
| 330 |
{ |
| 331 |
struct sdhci_pci_softc *sc = device_get_softc(dev); |
| 332 |
struct sdhci_slot *slot; |
| 333 |
uint32_t model; |
| 334 |
uint16_t subvendor; |
| 335 |
int bar, err, rid, slots, i; |
| 336 |
|
| 337 |
model = (uint32_t)pci_get_device(dev) << 16; |
| 338 |
model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; |
| 339 |
subvendor = pci_get_subvendor(dev); |
| 340 |
/* Apply chip specific quirks. */ |
| 341 |
for (i = 0; sdhci_devices[i].model != 0; i++) { |
| 342 |
if (sdhci_devices[i].model == model && |
| 343 |
(sdhci_devices[i].subvendor == 0xffff || |
| 344 |
sdhci_devices[i].subvendor == subvendor)) { |
| 345 |
sc->quirks = sdhci_devices[i].quirks; |
| 346 |
break; |
| 347 |
} |
| 348 |
} |
| 349 |
sc->quirks &= ~sdhci_quirk_clear; |
| 350 |
sc->quirks |= sdhci_quirk_set; |
| 351 |
|
| 352 |
/* Some controllers need to be bumped into the right mode. */ |
| 353 |
if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) |
| 354 |
sdhci_lower_frequency(dev); |
| 355 |
/* Read slots info from PCI registers. */ |
| 356 |
slots = pci_read_config(dev, PCI_SLOT_INFO, 1); |
| 357 |
bar = PCI_SLOT_INFO_FIRST_BAR(slots); |
| 358 |
slots = PCI_SLOT_INFO_SLOTS(slots); |
| 359 |
if (slots > 6 || bar > 5) { |
| 360 |
device_printf(dev, "Incorrect slots information (%d, %d).\n", |
| 361 |
slots, bar); |
| 362 |
return (EINVAL); |
| 363 |
} |
| 364 |
/* Allocate IRQ. */ |
| 365 |
i = 1; |
| 366 |
rid = 0; |
| 367 |
if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) |
| 368 |
rid = 1; |
| 369 |
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, |
| 370 |
RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); |
| 371 |
if (sc->irq_res == NULL) { |
| 372 |
device_printf(dev, "Can't allocate IRQ\n"); |
| 373 |
pci_release_msi(dev); |
| 374 |
return (ENOMEM); |
| 375 |
} |
| 376 |
/* Scan all slots. */ |
| 377 |
for (i = 0; i < slots; i++) { |
| 378 |
slot = &sc->slots[sc->num_slots]; |
| 379 |
|
| 380 |
/* Allocate memory. */ |
| 381 |
rid = PCIR_BAR(bar + i); |
| 382 |
sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, |
| 383 |
&rid, RF_ACTIVE); |
| 384 |
if (sc->mem_res[i] == NULL) { |
| 385 |
device_printf(dev, |
| 386 |
"Can't allocate memory for slot %d\n", i); |
| 387 |
continue; |
| 388 |
} |
| 389 |
|
| 390 |
slot->quirks = sc->quirks; |
| 391 |
|
| 392 |
if (sdhci_init_slot(dev, slot, i) != 0) |
| 393 |
continue; |
| 394 |
|
| 395 |
sc->num_slots++; |
| 396 |
} |
| 397 |
device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); |
| 398 |
/* Activate the interrupt */ |
| 399 |
err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, |
| 400 |
NULL, sdhci_pci_intr, sc, &sc->intrhand); |
| 401 |
if (err) |
| 402 |
device_printf(dev, "Can't setup IRQ\n"); |
| 403 |
pci_enable_busmaster(dev); |
| 404 |
/* Process cards detection. */ |
| 405 |
for (i = 0; i < sc->num_slots; i++) { |
| 406 |
sdhci_start_slot(&sc->slots[i]); |
| 407 |
} |
| 408 |
|
| 409 |
return (0); |
| 410 |
} |
| 411 |
|
| 412 |
static int |
| 413 |
sdhci_pci_detach(device_t dev) |
| 414 |
{ |
| 415 |
struct sdhci_pci_softc *sc = device_get_softc(dev); |
| 416 |
int i; |
| 417 |
|
| 418 |
bus_teardown_intr(dev, sc->irq_res, sc->intrhand); |
| 419 |
bus_release_resource(dev, SYS_RES_IRQ, |
| 420 |
rman_get_rid(sc->irq_res), sc->irq_res); |
| 421 |
pci_release_msi(dev); |
| 422 |
|
| 423 |
for (i = 0; i < sc->num_slots; i++) { |
| 424 |
sdhci_cleanup_slot(&sc->slots[i]); |
| 425 |
bus_release_resource(dev, SYS_RES_MEMORY, |
| 426 |
rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); |
| 427 |
} |
| 428 |
if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) |
| 429 |
sdhci_restore_frequency(dev); |
| 430 |
return (0); |
| 431 |
} |
| 432 |
|
| 433 |
static int |
| 434 |
sdhci_pci_shutdown(device_t dev) |
| 435 |
{ |
| 436 |
struct sdhci_pci_softc *sc = device_get_softc(dev); |
| 437 |
|
| 438 |
if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) |
| 439 |
sdhci_restore_frequency(dev); |
| 440 |
return (0); |
| 441 |
} |
| 442 |
|
| 443 |
static int |
| 444 |
sdhci_pci_suspend(device_t dev) |
| 445 |
{ |
| 446 |
struct sdhci_pci_softc *sc = device_get_softc(dev); |
| 447 |
int i, err; |
| 448 |
|
| 449 |
err = bus_generic_suspend(dev); |
| 450 |
if (err) |
| 451 |
return (err); |
| 452 |
for (i = 0; i < sc->num_slots; i++) |
| 453 |
sdhci_generic_suspend(&sc->slots[i]); |
| 454 |
return (0); |
| 455 |
} |
| 456 |
|
| 457 |
static int |
| 458 |
sdhci_pci_resume(device_t dev) |
| 459 |
{ |
| 460 |
struct sdhci_pci_softc *sc = device_get_softc(dev); |
| 461 |
int i, err; |
| 462 |
|
| 463 |
for (i = 0; i < sc->num_slots; i++) |
| 464 |
sdhci_generic_resume(&sc->slots[i]); |
| 465 |
err = bus_generic_resume(dev); |
| 466 |
if (err) |
| 467 |
return (err); |
| 468 |
if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) |
| 469 |
sdhci_lower_frequency(dev); |
| 470 |
return (0); |
| 471 |
} |
| 472 |
|
| 473 |
static void |
| 474 |
sdhci_pci_intr(void *arg) |
| 475 |
{ |
| 476 |
struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; |
| 477 |
int i; |
| 478 |
|
| 479 |
for (i = 0; i < sc->num_slots; i++) |
| 480 |
sdhci_generic_intr(&sc->slots[i]); |
| 481 |
} |
| 482 |
|
| 483 |
static device_method_t sdhci_methods[] = { |
| 484 |
/* device_if */ |
| 485 |
DEVMETHOD(device_probe, sdhci_pci_probe), |
| 486 |
DEVMETHOD(device_attach, sdhci_pci_attach), |
| 487 |
DEVMETHOD(device_detach, sdhci_pci_detach), |
| 488 |
DEVMETHOD(device_shutdown, sdhci_pci_shutdown), |
| 489 |
DEVMETHOD(device_suspend, sdhci_pci_suspend), |
| 490 |
DEVMETHOD(device_resume, sdhci_pci_resume), |
| 491 |
|
| 492 |
/* Bus interface */ |
| 493 |
DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), |
| 494 |
DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), |
| 495 |
|
| 496 |
/* mmcbr_if */ |
| 497 |
DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), |
| 498 |
DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq), |
| 499 |
DEVMETHOD(mmcbr_tune, sdhci_generic_tune), |
| 500 |
DEVMETHOD(mmcbr_retune, sdhci_generic_retune), |
| 501 |
DEVMETHOD(mmcbr_request, sdhci_generic_request), |
| 502 |
DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), |
| 503 |
DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), |
| 504 |
DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), |
| 505 |
|
| 506 |
/* SDHCI accessors */ |
| 507 |
DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), |
| 508 |
DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), |
| 509 |
DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), |
| 510 |
DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), |
| 511 |
DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), |
| 512 |
DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), |
| 513 |
DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), |
| 514 |
DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), |
| 515 |
DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing), |
| 516 |
|
| 517 |
DEVMETHOD_END |
| 518 |
}; |
| 519 |
|
| 520 |
static driver_t sdhci_pci_driver = { |
| 521 |
"sdhci_pci", |
| 522 |
sdhci_methods, |
| 523 |
sizeof(struct sdhci_pci_softc), |
| 524 |
}; |
| 525 |
static devclass_t sdhci_pci_devclass; |
| 526 |
|
| 527 |
DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, |
| 528 |
NULL); |
| 529 |
MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); |
| 530 |
|
| 531 |
#ifndef MMCCAM |
| 532 |
MMC_DECLARE_BRIDGE(sdhci_pci); |
| 533 |
#endif |
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